Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits and memory cells. The functional demands placed on these circuits and memory cells require the use of an ever-increasing number of linked transistors. As the number of transistors required increases, the surface space on the silicon chip/die that is allocated to each transistor dwindles. It is desirable then, to construct transistors which occupy less surface area on the silicon chip/die.
Typically, the memory cells of dynamic random access memories (DRAMs) include two main components, a field-effect transistor (FET) and a capacitor which functions as a storage element. The need to increase the storage capability of semiconductor memory devices has led to the development of very large scale integrated (VLSI) processes capable of creating smaller and smaller features. This reduction of feature size provides a substantial increase in density of memory cells in a DRAM.
The effort of extending DRAM cell density beyond the 1 gigabit generation presents the challenge of providing adequate cell capacitance within the projected cell area. Since capacitance is directly related to the surface area of the capacitor's plates, decreasing feature sizes make it very difficult to maintain sufficient cell capacitance. A cell capacitance of greater than or equal to twenty-five femto farads (.gtoreq.25 fF) is typically required in order to provide an adequate signal for sensing the stored charge over and above the anticipated noise levels. As memory cells are constructed to save precious chip space, they need to be configured in such a manner that the same data information can be stored and accessed.
An attractive means of maintaining the required storage ability is to implement a gain cell which provides an output current rather than a charge. Current sensing offers greater noise immunity and faster operation times than the conventional charge sense amplifier latch. One approach to this has been to provide a conventional, planar one transistor DRAM cell configuration to store charge on a planar diffused junction storage node. This node acts in turn as the gate of a lateral junction field-effect transistor (JFET) which is used to read the cell charge state.
An alternate approach is to construct a vertical cell with a surrounding gate write device wherein access to a read JFET is through a forward biased junction with the write bit line contact. The drawback to this method is that the forward biased junction causes the injection of minority carriers into the JFET channel which will then be collected largely by the storage node junction. Thus, the read operation of this device is destructive and transient.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory cell structure for dynamic random access memory devices which provide increased cell density while maintaining adequate cell capacitance and charge retention times. There is further need for such a memory cell structure offering these advantages along with a non-destructive read function.